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HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
Integrated Device Technology, Inc.
IDT7134SA/LA
FEATURES:
* High-speed access -- Military: 25/35/45/55/70ns (max.) -- Commercial: 20/25/35/45/55/70ns (max.) * Low-power operation -- IDT7134SA Active: 500mW (typ.) Standby: 5mW (typ.) -- IDT7134LA Active: 500mW (typ.) Standby: 1mW (typ.) * Fully asynchronous operation from either port * Battery backup operation--2V data retention * TTL-compatible; single 5V (10%) power supply * Available in several popular hermetic and plastic packages * Military product compliant to MIL-STD-883, Class B * Industrial temperature range (-40C to +85C) is available, tested to military electrical specifications
DESCRIPTION:
The IDT7134 is a high-speed 4K x 8 Dual-Port Static RAM designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to those
systems which cannot tolerate wait states or are designed to be able to externally arbitrate or withstand contention when both sides simultaneously access the same Dual-Port RAM location. The IDT7134 provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. It is the user's responsibility to ensure data integrity when simultaneously accessing the same memory location from both ports. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these Dual-Port typically on only 500mW of power. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200W from a 2V battery. The IDT7134 is packaged on either a sidebraze or plastic 48-pin DIP, 48-pin LCC, 52-pin PLCC and 48-pin Ceramic Flatpack. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
R/WL
CEL
R/WR
CER
OEL
I/O0L- I/O7L COLUMN I/O COLUMN I/O
OER
I/O0R- I/O7R
A0L- A11L
LEFT SIDE ADDRESS DECODE LOGIC
MEMORY ARRAY
RIGHT SIDE ADDRESS DECODE LOGIC
A0R- A11R
2720 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2720/4
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IDT7134SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS(1,2)
R/WR N/C R/WL N/C A11R
R/WL A11L A10L A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O 2L I/O 3L I/O 4L I/O 5L I/O 6L I/O 7L GND
OEL
I/O4L I/O5L
N/C GND
I/O0R I/O1R
I/O2R
I/O4R I/O5R
2720 drw 02
I/O3R
I/O6R
I/O6L I/O7L
1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 IDT7134 40 10 P48-1 39 & 11 38 12 C48-2 37 DIP 13 36 14 35 TOP 15 VIEW (3) 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25
CER
INDEX
R/WR A11R A10R
A0L
765 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 8 9 10 11 12 13 14 15 16 17 18
43
2
CEL
VCC
OER
1
52 51 50 49 48 47 46 45 44 43 42
A10R
A10L A11L
CER
OEL
VCC
CEL
OER
A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R N/C I/O7R
A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R
IDT7134 J52-1 PLCC TOP VIEW (3)
41 40 39 38 37 36
19 35 34 20 21 22 23 24 25 26 27 28 29 30 31 32 33
2720 drw 03
A10L A11L R/WL
R/WR
A11R
A10R
VCC
A0L
OER
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM
(2)
OEL
CER
CEL
INDEX
Rating Terminal Voltage with Respect to Ground Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
Com'l. -0.5 to +7.0
Mil. -0.5 to +7.0
Unit V
A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L
1 7 42 8 41 9 40 10 39 IDT7134 11 38 L48-1 & 12 37 F48-1 LCC/Flatpack 13 36 14 35 TOP VIEW (3) 15 34 16 33 17 32 18 31 19 20 21 22 23 24 25 26 27 28 29 30
GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O3L I/O4L I/O6L I/O7L I/O5L
65432
48 47 46 45 44 43
A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R
TA TBIAS TSTG PT(3) IOUT
0 to +70 -55 to +125 -55 to +125 1.5 50
-55 to +125 -65 to +135 -65 to +150 1.5 50
C C C W mA
2720 tbl 01
2720 drw 04
NOTES: 1. All Vcc pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. This text does not indicate orientation of actual part-marking.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 0.5V for more than 25%of the cycle time or 10 ns maximum, and is limited to < 20mA for the period of VTERM > Vcc +0.5V.
CAPACITANCE(1) (TA = +25C, f = 1.0MHz)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 3dv VOUT = 3dv Max. 11 11 Unit pF pF
2720 tbl 02
NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from 0V to 3V and from 3V to 0V.
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IDT7134SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Military Commercial Ambient Temperature -55C to +125C 0C to +70C GND 0V 0V VCC 5.0V 10% 5.0V 10%
2720 tbl 03
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0 -- -- Max. 5.5 0 6.0(2) 0.8 Unit V V V V
2720 tbl 04
NOTES: 1. VIL (min.) > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 0.5V.
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE (VCC = 5V 10%)
IDT7134SA Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Low Voltage Output High Voltage
(1)
IDT7134LA Min. -- -- -- -- 2.4 Max. 5 5 0.4 0.5 -- Unit A A V V V
2720 tbl 05
Test Conditions VCC = 5.5V, VIN = 0V to VCC
Min. -- -- -- -- 2.4
Max. 10 10 0.4 0.5 --
Output Leakage Current
CE = VIH, VOUT = 0V to VCC
IOL = 6mA IOL = 8mA IOH = -4mA
NOTE: 1. At Vcc 2.0V input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 5.0V 10%)
7134X20(4) Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) ISB1 Standby Current (Both Ports--TTL Level Inputs) ISB2 Standby Current (One Port--TTL Level Inputs) ISB3 Test Conditions Version Typ. MIL. S L -- -- 170 170 -- -- 25 25 -- -- 105 105 -- -- 1.0 0.2 -- -- 105 105
(2)
7134X25
(2)
7134X35
(2)
7134X45
(2)
7134X55
(2)
7134X70
Max. Typ. -- -- 280 240 -- -- 110 80 -- -- 180 150 -- -- 15 4.5 -- -- 170 130
Max. Typ. 310 150 260 150 280 150 220 150 100 80 80 50 210 170 180 140 30 10 15 4.0 210 150 170 120 25 25 25 25 85 85 85 85 1.0 0.2 1.0 0.2 85 85 85 85
Max. Typ. 300 140 250 140 260 140 210 140 75 55 75 45 200 160 170 130 30 10 15 4.0 190 130 160 110 25 25 25 25 75 75 75 75 1.0 0.2 1.0 0.2 75 75 75 75
Max. Typ. 280 240 240 200 70 50 70 40 190 150 160 130 30 10 15 4.0 180 120 150 100
Max. Typ.(2) Max. Unit 270 220 240 200 70 50 70 40 180 150 160 130 30 10 15 4.0 170 120 150 100 140 270 140 220 140 240 140 200 25 25 25 25 75 75 75 75 1.0 0.2 1.0 0.2 75 75 75 75 70 50 70 40 180 150 160 130 30 10 15 4.0 170 120 150 100 mA mA mA mA mA
CE = VIL
Outputs Open
160 160 160 160 25 25 25 25 95 95 95 95 1.0 0.2 1.0 0.2 95 95 95 95
140 140 140 140 25 25 25 25 75 75 75 75 1.0 0.2 1.0 0.2 75 75 75 75
f = fMAX(3)
COM'L. S L S L
CEL and CER = VIH MIL. f = fMAX(3) CE"A" = VIL and CE"B" = VIH
COM'L. S L MIL. S L
Active Port Outputs COM'L. S Open, f = fMAX(3) L S L
Full Standby Current Both Ports CEL and MIL. (Both Ports--All CER VCC - 0.2V CMOS Level Inputs) VIN VCC - 0.2V or VIN 0.2V, f = 0(3)
COM'L. S L MIL. S L
ISB4
Full Standby Current One Port CE"A" or (One Port--All CE"B" VCC - 0.2V
CMOS Level Inputs) VIN VCC - 0.2V or COM'L. S L VIN 0.2V Active Port Outputs Open, f = fMAX(3)
NOTES: 2720 tbl 06 1. "X" in part number indicates power rating (SA or LA). 2. VCC = 5V, TA = +25C for typical, and parameters are not production tested. 3. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby ISB3. 4. (Commercial only) 0C to +70C temperature range.
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IDT7134SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V
Symbol VDR ICCDR tCDR(3) tR
(3)
Parameter VCC for Data Retention Data Retention Current
Test Condition VCC = 2V
Min. 2.0 MIL. COM'L. -- -- 0 tRC
(2)
Typ.(1) -- 100 100 -- --
Max. -- 4000 1500 -- --
Unit V A
CE VHC
VIN VHC or < VLC
Chip Deselect to Data Retention Time Operation Recovery Time
ns ns
2720 tbl 07
NOTES: 1. VCC = 2V, TA = +25C, and are not production tested. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization, but not production tested.
DATA RETENTION WAVEFORM
DATA RETENTION MODE VCC 4.5V tCDR VDR 2V VDR 4.5V tR VIH
2720 drw 05
CE
VIH
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V Figures 1 and 2
2720 tbl 08
+5V 1250 DATAOUT 775 30pF *
2720 drw 06
+5V 1250 DATAOUT 775 5pF *
2720 drw 07
Figure 1. AC Output Test Load
Figure 2. Output Test Load (for tLZ, tHZ, tWZ, tOW) *Including scope and jig
6.04
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IDT7134SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(4)
7134X20(3) Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time
(1, 2) (1, 2) (2) (2)
7134X25 Min. 25 -- -- -- 0 0 -- 0 -- Max. -- 25 25 15 -- -- 15 -- 25
7134X35 Min. 35 -- -- -- 0 0 -- 0 -- Max. -- 35 35 20 -- -- 20 -- 35 Unit ns ns ns ns ns ns ns ns ns
Parameter
Min. 20 -- -- -- 0 0 -- 0 --
Max. -- 20 20 15 -- -- 15 -- 20
Output High-Z Time
Chip Enable to Power Up Time
Chip Disable to Power Down Time
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(4) (CONT'D)
7134X45 Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time
(1, 2) (1, 2)
7134X55 Min. 55 -- -- -- 0 5 -- 0 -- Max. -- 55 55 30 -- -- 25 -- 50
7134X70 Min. 70 -- -- -- 0 5 -- 0 -- Max. -- 70 70 40 -- -- 30 -- 50 Unit ns ns ns ns ns ns ns ns ns
2720 tbl 09
Parameter
Min. 45 -- -- -- 0 5 -- 0
(2)
Max. -- 45 45 25 -- -- 20 -- 45
Output High-Z Time
Chip Enable to Power Up Time(2) Chip Disable to Power Down Time
--
NOTES: 1. Transition is measured 500mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. (Commercial only) 0C to +70C temperature range only. 4. "X" in part number indicates power rating (SA or LA).
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(1, 2, 3)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATA VALID tOH DATA VALID
2720 drw 08
NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, OE or CE. 3. R/W = VIH.
6.04
5
IDT7134SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(1, 3)
tACE
CE
tAOE(4) tHZ(2)
OE
tLZ(1) DATAOUT tLZ(1) ICC CURRENT ISB tPU 50% tPD 50%
2720 drw 09
tHZ(2) VALID DATA (4)
NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, OE or CE. 3. R/W = VIH. 4. Start of valid data depends on which timing becomes effective , tAOE, tACE or tAA 5. tAA for RAM Address Access and tSAA for Semaphore Address Access.
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(6)
Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tWDD tDDD
NOTES:
Parameter Write Cycle Time Chip Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write RecoveryTime Data Valid to End-of-Write Output High-Z Time Data Hold Time
(1, 2) (3) (1, 2)
7134X20(5) Min. Max. 20 15 15 0 15 0 15 -- 0 -- 3 --
(4, 7)
7134X25 Min. Max. 25 20 20 0 20 0 15 -- 0 -- 3 -- -- -- -- -- -- -- -- -- 15 -- 15 -- 50 30
7134X35 Min. Max. 35 30 30 0 25 0 20 -- 3 -- 3 -- -- -- -- -- -- -- -- -- 20 -- 20 -- 60 35
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
2720 tbl 10
-- -- -- -- -- -- -- 15 -- 15 -- 40 30
Write Enabled to Output in High-Z Output Active from End-of-Write Write Pulse to Data Delay
(1, 2, 3)
(4)
Write Data Valid to Read Data Delay
--
1. Transition is measured 500mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 4. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read". 5. (Commercial only), 0C to +70C temperature range . 6. "X" in part number indicates power rating (SA or LA). 7. tDDD = 35ns for military temperature range.
6.04
6
IDT7134SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(6) (CONT'D)
Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tWDD tDDD Write Cycle Time Chip Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write RecoveryTime Data Valid to End-of-Write Output High-Z Time Data Hold Time(3) Write Enabled to Output in High-Z
(1, 2) (1, 2)
Parameter
7134X45 Min. Max. 45 40 40 0 40 0 20 -- 3 -- 3 --
(4)
7134X55 Min. Max. 55 50 50 0 50 0 25 -- 3 -- 3 -- -- -- -- -- -- -- -- -- 25 -- 25 -- 80 55
7134X70 Min. Max. 70 60 60 0 60 0 30 -- 3 -- 3 -- -- -- -- -- -- -- -- -- 30 -- 30 -- 90 70
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
2720 tbl 10
-- -- -- -- -- -- -- 20 -- 20 -- 70 45
Output Active from End-of-Write(1, 2, 3) Write Pulse to Data Delay
(4)
Write Data Valid to Read Data Delay
--
NOTES: 1. Transition is measured 500mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 4. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read". 5. (Commercial only), 0C to +70C temperature range . 6. "X" in part number indicates power rating (SA or LA).
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ (1)
tWC ADDR "A" MATCH tWP R/W "A" tDW DATAIN "A" VALID tAW
ADDR "B"
MATCH tWDD
DATAOUT "B" tDDD
NOTES: 1. Write cycle parameters should be adhered to, in order to ensure proper writing. 2. CEL = CER = VIL. OE"B" = VIL. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
VALID
2720 drw 10
6.04
7
IDT7134SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1, 5, 8) W
tWC ADDRESS tAS(6) tAW tWR(3) tHZ(7)
OE
CE
tWP(2) R/W tLZ DATAOUT
(4)
tWZ (7) tOW
(4)
tHZ(7)
tDW DATAIN
tDH
2720 drw 11
TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED TIMING(1, 5)
tWC ADDRESS tAW
CE
tAS(6) R/W tDW DATAIN
2720 drw 12
tEW(2)
1.20 in tWR(3)
tDH
NOTES: 1. R/W or CE must be High during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE =VIL and R/W = VIL. 3. tWR is measured from the earlier of CE or R/W going High to the end-of-write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal ( CE or R/W )is asserted last. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 500mV from steady state with the Output Test Load (Figure 2). 8. If OE is Low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
6.04
8
IDT7134SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
The IDT7134 provides two ports with separate control, address, and I/O pins that permit independent access for reads or writes to any location in memory. These devices have an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into standby mode when not selected (CE high). When a port is enabled, access to the entire memory array is permitted. Each port has its own Output Enable control (OE). In the read mode, the port's OE turns on the output drivers when set LOW. Non-contention READ/ WRITE conditions are illustrated in the table below.
TRUTH TABLE I - READ/WRITE CONTROL(2)
Left or Right Port(1) R/W W X X L H X
CE OE
H H L L X X X X L H
D0-7 Z Z DATAIN DATAOUT Z
Function Port Disabled and in Power Down Mode, ISB2 or ISB4
CER = CEL = H, Power Down
Mode, ISB1 or ISB3 Data on port written into memory Data in memory output on port High impedance outputs
2720 tbl 11
NOTES: 1. AOL - A11L AOR - A11R 2. "H" = HIGH, "L" = LOW, "X" = Don't Care, and "Z" = High-impedance
ORDERING INFORMATION
IDT XXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank B P C J L48 F 20 25 35 45 55 70 LA SA 7134 Commercial (0C to +70C) Military (-55C to +125C) Compliant to MIL-STD-883, Class B 48-pin Plastic DIP (P48-1) 48-pin Ceramic DIP (C48-2) 52-pin PLCC (J52-1) 48-pin LCC (L48-1) 48-pin Ceramic Flatpack (F48-1) Commercial Only Speed in nanoseconds
Low Power Standard Power 32K (4K x 8-Bit) Dual-Port RAM
2720 drw 13
6.04
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